MEMS (Microelectromechanical Systems) technology enables to fabricate microdevices with reduced size, weight, cost and power demanding, and yet with improved performance, functionality and reliability. In silicon micromachining, currently there is no fabrication technology available for the manufacture of virtually arbitrary, complex 3-D silicon microdevices. Therefore, current silicon microdevices suffer from fairly simple geometries defined only by one to five layers, i.e., either high-aspect-ratio 2.5-D structures by silicon bulk micromachining or low-aspect-ratio planar (2-D) structures by silicon surface micromachining, so that complex MEMS devices with high-performance are extremely hard to be realized.
The only way to realize relatively complex silicon microdevices is the bonding of pre-micromachined silicon microstructures, i.e., bulk micromachining plus silicon bonding. One well-known example is the micro gas turbine engine fabricated by bonding five layers of pre-micromachined silicon wafers (see Luc G. Fréchette et al, “High-Speed Microfabricated Silicon Turbomachinery and Fluid Film Bearings”, Journal of Microelectromechanical Systems, Vol. 14, No. 1, pp. 141-152 (2005)). However, this technology has its intrinsic drawbacks and is only suitable for building devices with limited 3-D geometries. The drawbacks are summarized as follows.
If we divide a truly 3-D microdevice into multiple layers along its z-axis, we will find that one or more of the layers comprise discrete features. A discrete feature means that it does not mechanically connect with other features on the same layer. Obviously this kind of layer cannot be made separately as discrete features will fall down. This is a fundamental drawback in bulk micromachining plus silicon bonding. To overcome this technical barrier, special fabrication approaches have to be implemented. For example, for making the layers containing discrete features, one solution is to use temporary silicon connections which support discrete silicon features. After all layers are bonded together, the temporary silicon connections are then cut to release the discrete features. However, this post-treatment only works for special designs. In addition, it is not a reliable and desirable approach as the removal of the mechanical connections is the last step of the process. If it fails, all previous work will be wasted. To avoid making the layers containing discrete features, one solution is to do multiple etching on both sides of layers. However, deep etching can be performed only once on each side of a layer, which restricts to form more complex structures. Besides, this solution involves many process steps and faces difficult operations, low throughput and low yield.
Another intrinsic drawback of this technology (bulk micromachining plus silicon bonding) is related to deep etching processes such as DRIE (Deep Reactive Ion Etching). The DRIE etch rate distributes non-uniformly both locally and globally over a wafer depending on feature geometry and feature distribution. Although the etch parameters of DRIE can be adjusted to an extent to lessen this effect, non-uniformity cannot be avoided. In addition, after DRIE, one has to accept as-is for both etched depth non-uniformity and etched surface smoothness since there does not exist a post-treatment process for improving non-uniformity and smoothness.
Summarily, although bulk micromachining plus silicon bonding is the way to form complex silicon microstructures, the intrinsic drawbacks of this technology restrict it to build limited 3-D microstructures and make it a quite complicated and low yield process as well. Because of the limitations of current silicon micromachining technologies, microdevices have to be designed to fit into the capabilities of silicon micromachining so that desired features have to be compromised or even sacrificed, and optimal performance usually cannot be achieved.
The present inventor invented a technique for forming multi-layer 3-D structures (e.g., parts, components, devices, and the like) by separately fabricating a plurality of individual layers and/or individual groups of layers of fabrication materials and then attaching them together. This technique is dubbed as Assemblayer™. It was disclosed in U.S. Non-Provisional patent application Ser. No. 11/278,137 filed Mar. 30, 2006 and U.S. Non-Provisional patent application Ser. No. 11/548,207 filed Oct. 10, 2006 by the present inventor. These two applications are hereby incorporated herein by reference as if set forth in full herein.
The Assemblayer™ technique applies the concept of Rapid Prototyping (RP) or Solid Freeform Fabrication (SFF) to multi-layer 3-D microfabrication in which an object with arbitrary 3-D geometry can be made by stacking a series of 2-D layers. As one or more of the 2-D layers may contain discrete features, a sacrificial material is thus used to function as an “adhesive” which combines the discrete features together on each of these layers. Otherwise the layers containing discrete features cannot be made. It is this unique use of sacrificial material that not only makes it possible to make 2-D layers containing discrete features, but also distinguishes Assemblayer™ from other microfabrication technologies. Unlike RP or SFF, the core of Assemblayer™ is to fabricate a plurality of individual layers and/or individual groups of layers of fabrication materials wherein at least one of the layers comprises at least one structural material and at least one sacrificial material. The structural material features on the layers compose desired 3-D microstructures. These layers are then aligned (if necessary) and attached together to form a multilayer structure. Finally the sacrificial material is removed to release the desired multi-layer 3-D structures. Note that in some cases if a sacrificial material does not influence what a multi-layer structure is designed to do, part or all of it may be left untouched.
When Assemblayer™ is used to fabricate structures comprising silicon, the resulting manufacturing process is dubbed as Si-Assemblayer™.